The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, for example, those suited for use in a semiconductor device having a vertical junction field effect transistor (JFET).
For example, U.S. Patent No. 20100148186 (Patent Document 1) describes a vertical JFET having a region equipped with sloped sidewalls which taper inward. These sidewalls form an angle of 5° or more from a vertical plane to the surface of a substrate. Since sidewall doping can be conducted without angled ion implantation, a vertical JFET having a uniformly and sufficiently controlled channel width can be formed according to this document.
Japanese Patent Laid-Open No. 2003-209263 (Patent Document 2) describes the structure of a vertical JFET having n+ type drain semiconductor portions and p+ type drain semiconductor portions and a method of manufacturing it. A channel semiconductor portion is located between the p+ type gate semiconductor portions and is controlled by the p+ type gate semiconductor portions.
Japanese Patent Laid-Open No. 2010-147405 (Patent Document 3) describes a normally off JFET capable of having improved breakdown voltage and reduced on resistance by introducing an impurity into the vicinity of a pn junction between a gate region and a channel region.
[Patent Documents]
    [Patent Document 1] U.S. Patent No. 20100148186    [Patent Document 2] Japanese Patent Laid-Open No. 2003-209263    [Patent Document 3] Japanese Patent Laid-Open No. 2010-147405